1. Technical Field
The present invention relates to a signal processing circuit which generates address data in accordance with data processing and reads out data stored in an external memory (based on the address data) for performing predetermined processing, and which generates address data in accordance with processed data and writes the processed data in the external memory in accordance with the address data.
2. Related Art
FIG. 6 shows a structure of a related art signal processing circuit 200. The signal processing circuit 200 is composed of a signal processing section 210 which performs predetermined signal processing and a memory access section 220 which writes data and address data generated by the signal processing section 210 in SDRAM (Synchronous Dynamic Random Access Memory) 100 and also reads data from the SDRAM 100 based on the address data generated by the signal processing section 210. The signal processing circuit 200 is formed on a single semiconductor substrate and is connected to the SDRAM 100.
The signal processing section 210 includes an address generation section 212 which generates address data for access to the SDRAM 100. The signal processing section 210 can be configured to decode video data such as Mpeg (Moving picture experts group), and the address generation section 212 generates address data suitable for the video data format.
The address generation section 212 generates row address data and column address data in accordance with data to be processed by the signal processing section 210, and also generates command data for access to the SDRAM 100. The command data includes, for example, an ACT command for designating a row address for access to the SDRAM 100, a WR command for writing data in the SDRAM 100 by designating a column address of the SDRAM 100, and an RD command for reading data from the SDRAM 100 by designating a column address of the SDRAM 100.
The memory access section 220 includes a register 222 which temporarily stores the command data and the address data generated by the address generation section 212 and a data interface (I/F) 240 which temporarily stores data read from the SDRAM 100 or data to be written in the SDRAM 100 to control reading and writing of data. The memory access section 220 is connected with the SDRAM 100 to output the command data and the address data stored in the register 222 to each of a plurality of terminals of the SDRAM 100 and to perform reading and writing of data with respect to the SDRAM 100 in accordance with the address data output from the register 222.
The SDRAM 100 is a memory cell array formed by row addresses and column addresses. The SDRAM 100 performs data reading and data writing operations in accordance with the command data and the address data output from the memory access section 220. The detailed structure of the SDRAM 100 will be described below.
Mpeg video signals, for example, are decoded in units of pixel blocks each formed of 8×8 pixels. If the SDRAM 100 has a storage capacity of 256 Mbits (16 Mwords×16 bits), in which case the SDRAM 100 is controlled by 13-bit row address data and 9-bit column address data, the address generation section 212 generates 13-bit row address data and 9-bit column address data in accordance with the of 8×8 pixels data format for access to the SDRAM 100.
If the signal processing circuit 200 is a circuit for decoding Mpeg video signals with high quality, it is necessary for the signal processing circuit 200 to process a larger amount of data with the increase in the image quality. Consequently, the signal processing circuit 200 requires the SDRAM 100 which is capable of storing a larger amount of data.
Here, when the SDRAM 100 having a large storage capacity is provided, the number of bits of the row address data and the column address data is changed with the increase in the storage capacity. If the storage capacity of the SDRAM 100 is increased to 512 Mbits (32 Mwords×16 bits), for example, it is necessary to control such an SDRAM 100 with 13-bit row address data and 10-bit column address data.
Accordingly, even if a 512 Mbit SDRAM 100 is connected with the conventional signal processing circuit 200 which includes the address generation circuit 212 which complies with the 256 Mbit SDRAM 100, it is not possible to use the entire storage region of the 512 Mbit SDRAM 100. Therefore, when developing a signal processing circuit which complies with a 512 Mbit SDRAM 100, it is necessary to design a new address generation section which generates 13-bit row address data and 10-bit column address data in accordance with the 8×8 pixels data format, resulting in an increase in the costs for the signal processing circuit associated with the increased development costs.